Semiconductor manufacturing techniques are cost effective because many die can be mass produced from a single wafer. First, the wafer is processed to create the various components of each die. Then, the wafer is separated into individual die, which each are packaged into the final integrated circuit.
Depending on the nature of the die, problems can arise during the separation of the wafer into die. Many conventional separation methods involve some sort of sawing, which is a "wet" process likely to cause damage to liquid-sensitive elements. Also, the separation can result in contamination of the die by debris resulting from the separation process. Some die are more susceptible to these types of damage than others, especially die having micromechanical elements that must have freedom of motion.
In the case of micromechanical devices, the wafer manufacturing process often includes formation of a "sacrificial layer" between other layers of the wafer. For these devices, one approach to eliminating damage during die separation is to retain the sacrificial layer while the wafer is being sawn into die. However, this requires the sacrificial layer to be removed from each die as a separate piece, instead of being removed at the wafer level. This die-level processing is time consuming and expensive. Also, steps that must follow removal of the sacrificial layer, such as passivation and testing, are more efficiently done at the wafer level.
U.S. patent application Ser. No. 08/001378, entitled "Integrated Partial Sawing Process", describes a technique for partially sawing a wafer before breaking it. The method includes covering the "streets" created by the partial sawing with a protective material.